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zhuyue

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How to expand the IO number for programmble controller using the self-defined communication protocol

Background

Our Wi-Fi IO module customer recently raised a special demand, an AGV integration needs to use 20 digital inputs.
One module only has 12 digital outputs in NPN format, as well as 8 fixed NPN/dry contacts and 6 configurable NPN/PNP/dry contacts, totally 14 digital inputs;
The problem is that, due to cost consideration, the Wi-Fi IO module does not reserve RS485 and other communication interfaces, and even more coincidentally, the output and input interfaces are not connected to the UART port of the microcontroller.
As a senior engineer with rich experience in the field of industrial control and IoT, these problems are obviously not difficult to defeat me.
After a simple analysis, I designed a solution;

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Communication Protocol

In order to achieve data communication between the modules through the input and output ports, I defined a set of communication protocols.
Bit ‘0’ is represented by a high/low level of duration T, bit ‘1’ is represented by a high/low level of duration T, and bit ‘1’ is represented by a high/low level of duration T.
Bit ‘1’ is represented by a high/low level with a duration of 2T.
A byte consists of 8 Bits of data bits, each of which flips the level;
A data frame consists of two bytes of frame header 55FF, one byte of data length, and N bytes of Payload, one byte of CRC checksum, leaving 5T frame interval between frames;
Communication Processing
Use the external interrupt of MCU's IO port to receive data.
At the same time, enable the rising and falling edge interrupts of the IO port, enable a timer for timing, and execute the interrupt procedure when the level change of the IO port occurs, in which the timing value of the current timer is obtained, and the difference between the timing value and the timing value of the last time the interrupt was entered is calculated.
If the difference is >1.5T, it means that the current received data bit is 1, otherwise it is 0. The current received data bit is cached, and when a Byte of data is received, it is sent to the receive ring queue for the main program to parse the data frame;
Use the system's Tick Clock interrupt for sending data, in the Tick Clock interrupt with a period of 250us to determine if there is any data to send, if there is a need to send data, a byte variable is counted, and the bit that is sent is a 1, then when the count value is a 2, the IO port is flipped, otherwise when the count value is a 1, the IO port is flipped;
With the addition of this communication protocol, the whole set of code enables only the Tick clock and external interrupts.
The Tick clock interrupt occurs at 250us, and in this interrupt routine, only some simple time timing and data sending are done, and for the STM32F103 processor with 72MHz selected as the main frequency, the worst case running time is about 5us;
The external interrupts also occur at 250us, and the worst-case running time is also about 5us;
The worst-case interrupt load factor is 10/250 = 4%, according to the Ford SDS requirements, the load factor must be less than 30%;

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While the main program has no dead wait operation, the worst case cycle time is about 600us, in the software function of the device, the input detection is designed according to the worst 2ms operation cycle, after considering the interrupt influence, the worst case load rate of the processor is 600/0.96/2000=31%;
There is a risk of failure, if the communication input signal contains interfering signals, causing the IO port to generate high frequency signal flip-flops, the MCU will enter external interrupts frequently, the occurrence cycle can be much less than 250us, and the processor will be busy with external interrupt routines, which will lead to other functional abnormalities;
According to Ford's requirements, this situation requires the addition of a low-pass filter in the external signal input circuit, and the change in the signal edge caused by the filter has been analysed by WCCA, and in the worst case the time consumed to rise from 10% to 90%, or to fall from 90% to 10%, is less than 10% of the time of the data bits;

Hardware Processing

There are several factors affecting the data waveform, i.e. pulse, throughout the hardware loop:
1) The response time of the Darlington transistor MJD122 used for the output, which, from the specifications, has a rise and fall time of 10us, which has a negligible effect on the data with a minimum pulse width of 250us;
(2) The response time of the optocoupler, from the specification, has a typical value of 4us and a maximum value of 18us;
(4) The charging and discharging time of the input and output parasitic capacitors of the optocoupler, the input capacitance is 150pF at maximum, the input resistance is 3.3kΩ, and the time constant is 0.5nS, which has little effect, but from the curves of the load resistance and the response time, it can be seen that the resistance value of the load resistor has an effect on the rise and fall time.

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And according to the module input detection circuit, as shown in the following figure:

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When the NPN input is low, the optocoupler is turned on, and the LED D47 is also turned on. At this time, the load resistance of the optocoupler is approximately R106 and the internal pull-up resistance of the MCU, which is about 3.0K (3.3K//40K), the fall time is about 40us. When the NPN input is high impedance, the optocoupler is turned off, and the LED D47 is also turned off. At this time, the load resistance of the optocoupler is the internal pull-up resistance of the MCU, which is maximum around 50K, the rise time will be more than 100us;

For a 250 us pulse width of bit 0, a change of more than 125 us will occur, which exceeds the judgment threshold of bit 1 by 375 us, causing it to be misjudged as bit 1, resulting in an error code and causing communication anomalies.

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The optical coupler output waveform when D47 is not short-circuited.

To solve this problem, I short-circuited D47, so that the load resistance when the optical coupler is turned off becomes 3.0KΩ, and communication resumes to normal.

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Short-circuit the output waveform of the D47 optical coupling.

At worst, because the response time and load resistance curves are data at ambient temperature, if a 2x safety margin is considered, the rise and fall times can be up to 80 us. The delay of the Darlington transistor is calculated at 20 us, which leads to a pulse variation of 100 us. Additionally, consider a 5 us interrupt response time;

The pulse width of BIT0 will be increased from a maximum of 250 us to 355 us, leaving a margin of 20 us compared to the judgment threshold value of 375 us, which should ensure reliable reception.

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