Some time ago, I mentioned the IF electrostatic precipitator controller, I carefully analyzed the single-phase and three-phase SPWM drive time, completed the SPWM code writing on the STM32F103 processor, and tested the signals and waveforms with an oscilloscope and a logic analyzer.
The TIMER1 and TIMER2 of STM32F103 support complementary PWM outputs, and I chose CH1,CH2,CH3 of TIMER1 for A,B,C three-phase drive;
The clock frequency of the processor is 72MHz, and the dead time of the complementary PWM output is set to 4us by the following code;
SPWM_PWM_TIMER->BDTR = 0x80C4.
A half-cycle sinusoidal data table is generated, and based on the frequency of the sinusoidal signal and the value of the frequency of the PWM, the intervals in which the period of the sinusoidal signal needs to be divided are calculated, the average value of each sinusoidal signal data is calculated, and the duty cycle value of each interval is calculated based on the maximum sinusoidal data, and maximum duty cycle values of PWM signal;
When the frequency of the SPWM is 10kHz and the frequency of the sine signal is 50Hz, the output SPWM signal will be passed through two stages of low-pass filtering resistors with 1kΩ resistor + 0.1uF capacitor, and I can see a very perfect sine signal.
At first, I wanted to automatically set the duty cycle value calculated by SPWM to the CCR register of TIMER through DMA and realize the update of DMA cache in half-completion interrupt and completion interrupt, but because the frequency may also change during operation, which will lead to the dynamic change of the number of data in DMA, making the output of the sinusoidal signal of SPWM output incoherent and generating a high-frequency component.
Finally, the three-phase CCR register values are updated for each cycle of the PWM signal through the update interrupt of TIMER.
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